The invention relates generally to data storage systems, communication systems and other types of systems which incorporate a Viterbi algorithm decoding process or other decoding process involving the processing of error events, and more particularly to parity-check coding techniques suitable for use in conjunction with channel coding in such systems.
Channel coding is a conventional technique commonly used to increase the robustness of a data storage system or digital communication system. This technique is used in data storage applications such as the processing of data for storage on magnetic or optical disks. Channel coding is also used in many different types of communication systems, including voice-band modems, Asymmetric Digital Subscriber Line (ADSL) systems, audio broadcasting systems, Fast or Gigabit Ethernet systems, cellular systems and wireless local loop systems.
The principle underlying channel coding is to introduce redundancy and memory into a transmitted bit stream so as to facilitate error detection and correction at the decoder. Two general classes of channel codes are block codes and trellis codes. Block codes operate on a block-by-block basis, such that output code words depend only on the current input block message. Trellis codes, in contrast, may be viewed as mapping one arbitrarily long bit stream into another, with no assumed block structure.
One important category of block codes is the class of run-length limited (RLL) codes. The codewords of an RLL code are run-length limited binary sequences of a fixed length n, also known as (d,k) sequences, and are characterized by the parameters d and k, which indicate the minimum and maximum number of xe2x80x9czerosxe2x80x9d between consecutive xe2x80x9conesxe2x80x9d in the binary sequence, respectively. Such codes are typically used for high density recording channels in a data storage system.
Convolutional codes are a commonly-used linear class of trellis codes. In such codes, output codewords result from the convolution of an input message stream with the impulse response of an encoder which includes a v-stage shift register. A given n-bit code word is generated as a function of k input bits and v bits stored in the shift register. The constraint length K of the encoder is defined as k+v, and the rate of the code is given by k/n, where n greater than k. A convolutional encoder thus operates as a finite state machine with a maximum of 2v=2Kxe2x88x92m possible states. The k input bits cause a transition from a present state, defined by v bits, to the next state, and the number of output bits, i.e., code bits, produced depends on the rate of the code.
The Viterbi algorithm is an efficient maximum-likelihood sequence detection method for use in conjunction with the decoding of block or trellis codes transmitted over Additive White Gaussian Noise (AWGN) channels. The Viterbi algorithm is described in, e.g., A. J. Viterbi, xe2x80x9cError Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,xe2x80x9d IEEE Trans. on Information Theory, Vol. IT-13, April 1967; G. D. Forney, Jr., xe2x80x9cMaximum-likelihood sequence detection in the presence of intersymbol interference,xe2x80x9d IEEE Trans. on Information Theory, Vol. IT-18, pp. 363-378, May 1972; and G. D. Forney, Jr., xe2x80x9cThe Viterbi algorithm,xe2x80x9d IEEE Proceedings, Vol. 61, pp. 268-278, March 1973, all of which are incorporated by reference herein. The algorithm decodes received bits or symbols by finding the most likely path through a time-expanded state transition diagram called a trellis.
Parity-check codes are often utilized in conjunction with the above-described channel codes. For example, such parity-codes are often used for post-processing of error events generated by a maximum-likelihood sequence detector based on the Viterbi algorithm. More particularly, it is known in the art to utilize an m-bit parity check code in order to associate each of a number of dominant error events that may be generated by the Viterbi algorithm with a corresponding unique syndrome. In this manner, each of the dominant error events can be uniquely identified, and an appropriate corrected output can be generated for each error event. Additional details regarding conventional parity-check coding can be found in, e.g., Richard D. Gitlin et al., xe2x80x9cData Communications Principles,xe2x80x9d pp. 168-173, Plenum Press, New York, 1992, which is incorporated by reference herein.
Conventional parity-check coding has a number of significant disadvantages. For example, the use of an m-bit code to assign each error event a unique syndrome requires storage of a substantial list of syndrome-event pairs in a lookup table. Increasing the number of lookup table entries increases the complexity of the decoding process and the cost of the corresponding decoder. In addition, as the parity-check code word block size N increases and the operating signal-to-noise ratio (SNR) decreases, combinations of certain error events may produce common non-unique syndromes. In many applications it is desirable to utilize large parity-check code block lengths N with a relatively small number of parity-check code bits m in order to keep the parity-check code rate as high as possible. However, the number of available unique syndromes is given by 2m, such that limiting the number of parity-check bits m also limits the number of unique syndromes. In the presence of this higher amount of ambiguity, it is often necessary to choose from among several candidate error events one particular error event to be corrected, and there is only a limited probability of choosing the right candidate. The numerous non-unique syndromes in conventional m-bit parity-check coding can thus result in a large error miscorrection rate.
A need therefore exists for improved parity-check coding which can reduce the number of lookup table entries required, while also improving performance by increasing the probability of selecting the appropriate error event for correction.
The present invention provides improved parity-check coding for processing of Viterbi algorithm error events or other decoding-related error events in a data storage system, communication system or other type of system.
In accordance with the invention, a sequence of information bits are parity-check coded in a parity generator utilizing an m+1-bit parity-check code. The m+1-bit parity-check code may be formed as a combination of an otherwise conventional m-bit parity-check code and an overall parity bit. The additional overall parity bit provides an indication of the parity of a plurality of composite or single error events associated with decoding of the parity codewords. The parity generator includes a single-parity encoder for generating the overall parity bit, and a parity generator matrix element for generating a codeword based on the m-bit parity-check code, with a given one of the codewords of the m+1-bit parity-check code formed as a combination of the codeword based on the m-bit parity-check code and the overall parity bit. The invention can be used with any conventional m-bit parity-check code to produce an m+1-bit enhanced parity-check code with K=Nxe2x88x92m and rate             N      -      m              N      +      1        ,
where N+1 denotes the total number of bits in a given one of the m+1-bit parity codewords.
Advantageously, the invention results in substantial improvements in decoding complexity by reducing the number of required lookup table entries by a factor of one-half, which significantly decreases decoder memory requirements and access time. In addition, the invention significantly improves decoding performance by increasing the probability of choosing the appropriate error event for correction to thereby produce a lower error miscorrection rate.